1. Field of the Invention
The present invention relates to a half-rate clock and data recovery (CDR) circuit in which constituent elements operate at a half rate of 5 GHz equal to a half of a full rate of 10 GHz.
2. Description of the Prior Art
In response to recent high-speed trends of optical communication network, there is a demand for a CDR circuit operating at a data transfer rate of not less than 10 Gbits/sec. (Gbps). Conventionally, if a CDR circuit formed by CMOS process is operated at a high data transfer rate of not less than 10 Gbps, the constituent transistors should operate at the full rate of 10 GHz.
On the other hand, some receiver chips formed by the CMOS process are produced by a half-rate circuit technique so as to operate at the half rate of 5 GHz. This half-rate circuit technique is considered to be a technique necessary for operating the CDR circuit at high speed by the CMOS transistors.
FIG. 13 shows one example of a whole configuration of a conventional CDR circuit. The conventional CDR circuit includes a phase detector 110, a charge pump circuit 120, a low-pass filter (LPF) 130 and a voltage controlled oscillator (VCO) 140 which are connected to each other in series in this order. The phase detector 110 detects a phase difference between a reference signal Sref and an oscillation signal So fed back by the VCO 140 and outputs to the charge pump circuit 120 a signal Spd corresponding to the phase difference. The signal Spd from the phase detector 110 is converted into a ternary signal, i.e., a three-valued signal St by the charge pump circuit 120. Then, the LPF 130 integrates the ternary signal St from the charge pump circuit 120 so as to generate a control voltage Vc for controlling the VCO 140. Furthermore, the VCO 140 outputs to the phase detector 110 the oscillation signal So having a frequency corresponding to the control voltage Vc.
FIG. 14 is a circuit diagram of the phase detector 110 employed in the conventional CDR circuit of FIG. 13 and FIG. 15 is a timing chart of signals of the conventional phase detector 110. In FIG. 15, dotted lines indicate several waveforms which the signals of the conventional phase detector 110 can take. The conventional phase detector 110 includes first and second latch circuits 151 and 153, further first and second latch circuits 152 and 154, an exclusive OR circuit 155 for outputting an error signal Error and an exclusive OR circuit 156 for outputting a reference signal Ref. The first latch circuit 151 receives an input signal Data, an inverted input signal/Data and a half-rate clock CLK, while the further first latch circuit 152 receives the input signal Data, the inverted input signal/Data and an inverted half-rate clock/CLK. The second latch circuit 153 receives the inverted half-rate clock/CLK, while the further second latch circuit 154 receives the half-rate clock CLK.
As will be apparent from waveforms of the error signal Error and the reference signal Ref shown in FIG. 15, operating speed of the exclusive OR circuit 155 for the error signal Error is higher than that of the exclusive OR circuit 156 for the reference signal Ref. Pulses of hatched portions in the signals X1 and X2 in FIG. 15 are necessary for inputting to the exclusive OR circuit 155 a signal X1 outputted from an output terminal Q of the first latch circuit 151 and a signal X2 outputted from an output terminal Q of the further first latch circuit 152. Thus, the exclusive OR circuit 155 requires a full-rate switching speed in order to receive the full-rate pulses of the hatched portions in the signals X1 and X2. Hence, in the phase detector 110 of the conventional CDR circuit, the first latch circuit 151, the further first latch circuit 152 and the exclusive OR circuit 155 should operate at the full rate.
Therefore, in the conventional phase detector 110 shown in FIGS. 14 and 15, since the exclusive OR circuit should operate at the full rate, such a problem arises that operating margin is small.